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CY2272
Pentium(R), 6x86, K6 Clock Synthesizer/Driver for Mobile PCs with Intel(R) 82430TX or Ali IV/V+ and 3 SO-DIMMs
Features
* Mixed 2.5V and 3.3V operation * Complete clock solution for Pentium(R), Cyrix, and AMD processor-based motherboards -- Four CPU clocks at 2.5V or 3.3V with three dedicated CPU frequency select inputs -- Six 3.3V SDRAM clocks, support three portable DIMMs -- Seven synchronous PCI clocks, one free-running, one early -- One 3.3V 48 MHz USB clock -- One 3.3V 24 MHz IO clock -- Two high drive 3.3V Ref. clocks at 14.318 MHz * 1 ns-4 ns delay between CPU and PCI clocks * I2CTM Serial Configuration Interface * Factory-EPROM programmable output drive and slew rate for EMI customization * Factory-EPROM programmable CPU clock frequencies for custom configurations * Dedicated Power-down, CPU stop and PCI stop pins * Available in space-saving 48-pin SSOP package the PCI clocks by 1-4 ns. Additionally, the part outputs six 3.3V SDRAM clocks, one 3.3V USB clock at 48 MHz, one IO clock at 24 MHz, and two high-drive 3.3V reference clocks at 14.318 MHz. The part possesses dedicated power-down, CPU stop, and PCI stop pins for power management control. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2272 outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2272 Selector Guide
Clock Outputs CPU (13.75, 15, 16.6, 18.75, 55, 60, 66.6, 75 MHz) SDRAM PCI (CPU/2MHz) USB (48MHz) IO (24MHz) Ref (14.318MHz) CPU-PCI delay
Note: 1. One free-running PCI clock, one early PCI clock.
a
-1 4 6 7[1] 1 1 2 1-4 ns
Functional Description
The CY2272 is a clock synthesizer/driver for a Pentium, Cyrix 6x86, or AMD K6 processor-based mobile PC using Intel(R)'s 82430TX, Aladdin IV+ or other similar chipsets. The CY2272-1 outputs four CPU clocks at 2.5V or 3.3V. There are seven PCI clocks, running at one half the CPU clock frequency. One of the PCI clocks is free-running. Another leads
Logic Block Diagram
REF [0-1] (14.318 MHz)
14.318 MHz OSC. CPU PLL STOP LOGIC
Pin Configuration
SSOP Top View
AVDD REF0 VSS XTALIN XTALOUT REF1 VDDQ3 PCICLK_F VSS PCICLK0 PCICLK1 PCICLK2
XTALIN
XTALOUT
CPUCLK [0-3] VDDCPU
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDQ3 USBCLK IOCLK VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ3 CPU_STOP PCI_STOP VSS SEL0 SEL2
PWR_DWN SEL0 SEL1 SEL2 CPU_STOP
EPROM
SDRAM [0-5]
/2 or /2.5 SYS PLL
EPCICLK PCI_STOP
Delay STOP LOGIC
PCICLK3 VDDQ3 PCICLK4 VSS EPCICLK VSS VDDQ3 PWR_DWN SEL1 VSS SDATA SCLK
PCICLK [0-5] PCICLK_F USBCLK
SCLK SDATA
SERIAL INTERFACE CONTROL LOGIC
/2
IOCLK
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
CY2272-1
* 408-943-2600 October 12, 1998
CY2272
Pin Summary
Name VDDQ3 VDDCPU AVDD VSS XTALIN
[2]
Pins 7, 14, 19, 30, 36, 48 42 1 4 5 28 29 20 38, 37, 35, 34, 32, 31 26 21 25 44, 43, 41, 40 10, 11, 12, 13, 15 8 17 2, 6 47 46 23 24
Description 3.3V Digital voltage supply CPU Digital voltage supply, 2.5V or 3.3V Analog voltage supply, 3.3V Reference crystal input Reference crystal feedback Active LOW control input to stop PCI clocks (except free-running PCI clock) Active LOW control input to stop CPU clocks Active LOW control input to power down device SDRAM clock outputs CPU frequency select input, bit 0 (See table below.) CPU frequency select input, bit 1 (See table below.) CPU frequency select input, bit 2 (See table below.) CPU clock outputs PCI clock outputs, at one-half the CPU frequency Free-running PCI clock output Early PCI clock, leads PCI clocks by 1-4 ns 3.3V Reference clock outputs, drive 45-pF loads USB Clock output (48 MHz) IO Clock output (24 MHz) Serial data input for serial configuration port Serial clock input for serial configuration port
3, 9, 16, 18, 22, 27, 33, 39, 45 Ground
XTALOUT[2] PCI_STOP CPU_STOP PWR_DWN SDRAM[0-5] SEL0 SEL1 SEL2 CPUCLK[0:3] PCICLK[0:4] PCICLK_F EPCICLK REF[0-1] USBCLK IOCLK SDATA SCLK
Function Table, EPROM Programmable
I2C Bit 4 0 0 0 0 0 0 0 0 SEL0 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL2 0 1 0 1 0 1 0 1 CPU/PCI Ratio 2 2 2.5 2 2 2 2.5 2 CPUCLK[0:3] SDRAM[0:5] 15 MHz 16.67 MHz 18.75 MHz 13.75 MHz 60.0 MHz 66.67 MHz 75.0 MHz 55.0 MHz PCICLK[0:4] PCICLK_F EPCICLK 7.5 MHz 8.33 MHz 7.5 MHz 6.875 MHz 30.0 MHz 33.33 MHz 30.0 MHz 27.5 MHz REF[0-1] 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz USBCLK 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz 48 MHz IOCLK 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz 24 MHz
Note: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
2
CY2272
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK CPUCLK USBCLK IOCLK Target Frequency (MHz) 66.67 60.0 75.0 48.0 24.0 Actual Frequency (MHz) 66.654 60.0 75.0 48.008 24.004 0 0 167 167 PPM -195
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V.
Power Management Logic
CPU_STOP PCI_STOP X 0 0 1 1 X 0 1 0 1 PWR_DWN 0 1 1 1 1 CPUCLK Low Low Low PCICLK EPCICLK Low Low CPU PLL / 2 PCICLK_F Stopped Running Running Running Running Other Clocks Stopped Running Running Running Running Osc. Off PLLs Off
Running Running Running Running Running Running Running Running
As per Func. Tbl. Low As per Func. Tbl. As per Func. Tbl.
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2273 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ----
Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable)
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' Frequency Select (Refer to Freq. Sel. Table) (Reserved) drive to `0' (Reserved) drive to `0' Bit 1 1 1 0 0 Bit 0 1 - Three-State 0 - N/A 1 - Testmode 0 - Normal Operation Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0
Select Functions based on Byte 0
Outputs Functional Description Three-State Test Mode[4] Hi-Z TCLK/2[3] CPU PCI, PCI_F Hi-Z TCLK/4 SDRAM Hi-Z TCLK/2 Ref Hi-Z TCLK USBCLK Hi-Z TCLK/2 IOCLK Hi-Z TCLK/4
Notes: 3. TCLK supplied on the XTALIN pin in Test Mode. 4. Valid only for SEL2=1, SEL1=0, SEL0=1.
3
CY2272
Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 N/A N/A 40 41 43 44 Description USBCLK (Active/Inactive) IOCLK (Active/Inactive) (Reserved) drive to `0' Not used - drive to `0' CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -7 15 14 12 11 10 8 Pin # Description (Reserved) drive to `0' PCICLK_F (Active/Inactive) EPCICLK (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) Bit 7 28 Bit 6 29 Bit 5 31 Bit 4 32 Bit 3 34 Bit 2 35 Bit 1 37 Bit 0 38
Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A 17 18 20 21 Description Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0' Not used - drive to `0'
Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # N/A N/A N/A N/A N/A N/A 6 2 Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' REF1 (Active/Inactive) REF0 (Active/Inactive)
Byte 6: Reserved, for future use
4
CY2272
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[5]
Parameter AVDD, V DDQ3 VDDCPU TA CL CPU Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, USBCLK, IOCLK EPCICLK, PCICLK SDRAM REF [0,1] Reference Frequency, Oscillator Nominal Value Description Analog and Digital Supply Voltage Min. 3.135 2.375 3.135 0 10 30 20 20 14.318 Max. 3.465 2.9 3.465 70 20 30 30 45 14.318 MHz Unit V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Low-level Output Voltage Except Crystal Inputs Except Crystal Inputs I2C inputs only IOH = 16 mA CPUCLK IOL = 27 mA CPUCLK IOH = 16 mA CPUCLK IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 26 mA USBCLK IOCLK IOH = 36 mA REF[0-1] VOL Low-level Output Voltage VDDQ3, AV DD, VDDCPU = 3.135V IOL = 27 mA CPUCLK IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 21 mA USBCLK IOCLK IOL = 29 mA REF[0-1] IIH IIL IOZ IDD IDD IDDS Input High Current Input Low Current Output Leakage Current Power Supply Current Power Supply Current Power-down Current VIH = VDD VIL = 0V Three-state VDD = 3.465V, VIN = 0 or V DD, Loaded Outputs, CPU clocks = 66.67 MHz VDD = 3.465V, VIN = 0 or V DD, Unloaded Outputs Current draw in power-down state -10 -10 +10 10 +10 300 140 150 A A A mA mA A 0.4 V 2.4 2.0 0.4 VDDCPU = VDDQ2 = 2.375V Test Conditions Min. Max. Unit 2.0 0.8 0.7 V V V V V V
High-level Output Voltage VDDCPU = VDDQ2 = 2.375V High-level Output Voltage VDDQ3, AV DD, VDDCPU = 3.135V
Note: 5. Electrical parameters are guaranteed with these operating conditions.
5
CY2272
Switching Characteristics[6]
Parameter t1 t2 t2 t2 t2 t3 t4 t5 t6 t7 Output All CPUCLK REF[0-1] PCICLK, EPCICLK SDRAM CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM Description Output Duty Cycle
[7]
Test Conditions t1 = t1A / t1B
Min. Typ. 45 50
Max. 55 4.0 4.0 4.0 4.0 2.13 2.67 2.13 2.67
Unit % V/ns V/ns V/ns V/ns ns ns ps ns
CPU Clock Rising and Falling Edge Rate REF Clock Rising and Falling Edge Rate PCI, EPCI, Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew CPU-SDRAM Clock Skew
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.75 Between 0.4V and 2.4V, VDDCPU = 3.3V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 0.4V and 2.4V, VDDCPU = 3.3V Between 2.0V and 0.4V, VDDCPU = 2.5V Between 2.4V and 0.4V, VDDCPU = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, V DDCPU = 3.3V Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks - Measured at 66.66 MHz - Measured at 75 MHz. Measured at 1.5V Measured at 1.5V Measured at 1.5V for 3.3V clocks 1.0 2.0 1.0 0.75 0.9 0.9 0.4 0.5 0.4 0.5 100 2.0
250 4.0
650 750 250 350 4.0 400 300 400
ps ps ps ps ns ps ps ps ms
t8 t9 t10 t10 t11 t12
PCICLK, PCICLK EPCICLK, PCICLK CPUCLK[7] SDRAM[7] PCICLK, EPCICLK[7] CPUCLK, PCICLK, EPCI, SDRAM CPUCLK PCICLK SDRAM
PCI-PCI Clock Skew PCI-PCI_F Clock Skew EPCI-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
CPU, PCI, EPCI, and SDRAM clock stabilization from power-up
3
t13
/4 Frequency Slew Time
Time for CPU, EPCI, PCI, and SDRAM clock frequency to change from F to F/4 after select input change
10
25
cycles
Notes: 6. All parameters specified with maximum loaded outputs, measured with select lines = 101 and 110 (sel0, sel1, sel2). 7. Measured at 1.5V for 3.3V clocks and at 1.25V for 2.5V clocks.
6
CY2272
Timing Requirement for the I2C Bus
Parameter t12 t13 t14 t15 t16 t17 t18 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The LOW period of the clock. The HIGH period of the clock. Set-up time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters. for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns s ns s Max. 100 Unit kHz s s s s s s
t19 t20 t21 t22
Switching Waveforms
Duty Cycle Timing
t1A t1B
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3 t2 t4
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
7
CY2272
Switching Waveforms (continued)
CPU-SDRAM Clock Skew
CPUCLK
SDRAM t7
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
PCI-PCI Clock Skew
PCICLK
PCICLK t8
EPCI-PCI Clock Skew
EPCICLK
PCICLK t9
CPU_STOP[8, 9]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) Notes: 8. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles. 9. CPU_STOP may be applied asynchronously. It is synchronized internally.
8
CY2272
Switching Waveforms (continued)
PCI_STOP[10, 11]
CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External)
PWR_DOWN
CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
t13 SCL t14 t15
t20
t21
t14
t18
t16
t19
t17
t22
Notes: 10. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 11. PCI_STOP may be applied asynchronously. It is synchronized internally.
9
CY2272
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
10
CY2272
Test Circuit
VDDQ3
1 0.1 F 3
48 0.1 F 45
7 0.1 F 9 39 14 0.1 F 42 0.1 F
VDDCPU
CY2272
36
0.1 F
16
33 30
18
0.1 F 27
0.1 F
19
22
OUTPUTS CLOAD
Note: All Capacitors must be placed as close to the pins as is possible
Ordering Information
Ordering Code CY2272PVC-1 Document #: 38-00607-C Package Name O48 Package Type 48-Pin SSOP Operating Range Commercial
11
CY2272
Package Diagram
48-Lead Shrunk Small Outline Package O48
51-85061-B
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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